Large integrated circuits generally have a multi-level clock distribution network for providing clock signals to the clocked logic elements of the circuit. These networks are typically designed to be used with automated place and route design tools. In general, these clock distribution networks use several levels of buffers to distribute the clock signals to the clocked logic elements. Some automated place and route design tools attempt to equalize the clock line lengths and capacitive loading within each level of buffering. However, in conventional clock distribution schemes, the automated place and route design tools cannot efficiently route the clock lines from the lowest level of buffers to the clocked logic elements with low clock skew. As a result, the designer typically must hand tune the routing of the clock lines to the clocked logic elements at the lowest level of buffering. This hand tuning of the clock lines is necessary to reduce undesirable clock skew between the clocked logic elements.
For example, FIG. 1 shows an exemplary clock distribution network 100 having four levels of buffering for an integrated circuit 101. The clock distribution network 100 includes a phase locked loop (PLL) 103 connected to a first-level buffer 105. The PLL 103 receives a raw clock signal from an off chip source (not shown) and outputs a clock signal synchronized with the raw clock signal. The clock signal outputted by the PLL 103 can be of a different frequency of than the raw clock signal outputted by the PLL 103 can be of a different frequency of than the raw clock signal. The first-level buffer 105 drives, in this example, five second-level buffers 107A-107E. In addition, in this example, each second-level buffer 107A-107E drives five third-level buffers. For clarity, only the third-level buffers 109A-109E driven by the second-level buffer 107E are shown. The third-level buffers 109A-109E respectively drive a corresponding datapath blocks 111A-111E. Each datapath block includes a logic block with a relatively large number (up to several hundred) of clocked logic elements such as flip flops. Each datapath block also includes fourth-level buffers connected to receive the buffered clock signals from the third-level buffers. The datapath block's fourth-level buffers provide clock signals to the clocked logic elements within the datapath block's logic block.
FIG. 2 is an exemplary block diagram of the datapath block 111A shown in FIG. 1. The datapath block 111A includes a logic block 201 that has clocked logic elements distributed in N rows within the logic block, where N can be an integer greater than 1. The datapath block 111A also includes a buffer block 203 that includes fourth-level buffers 205.sub.1 -205.sub.N. These fourth-level buffers 205.sub.1 -205.sub.N are coupled to receive the buffered clock signal from the third-level buffer 109A (FIG. 1) and drive flip-flops 207. Each fourth-level buffer 205.sub.1 -205.sub.N respectively drives the flip-flops 207 located in a corresponding predefined area (i.e., a row in this embodiment) 209.sub.1 -209.sub.N. In this embodiment, the datapaths can be up to sixty-four bits wide. Consequently, the number of flip-flops in each row 209.sub.1 -209.sub.N can vary between one and sixty-four. As is well known in the art of clock distribution networks, the capacitive loading driven by a clock buffer depends on both the length of the driven clock line as well as the capacitive loading of each of the clocked logic elements connected to the clock line. Because the number of clocked logic elements and the clock line length within each row can vary, the capacitive load driven by each fourth-level buffer can vary. As a result, each fourth-level buffer 205.sub.1 -205.sub.N is typically custom designed to drive the particular capacitive load of its corresponding row 209.sub.1 -209.sub.N to equalize the clock skew in the datapath block. The required customization of the fourth-level buffers undesirably increases the complexity, time and expense of designing the clock distribution network. Also, the input capacitance of each of the custom fourth-level buffers may be different, thereby introducing further complexity in equalizing the clock skew between the third-level buffers 107A-107E (FIG. 1) and the datapath blocks. As a result, the designer may be required to go through several iterations of designing the clock distribution network to achieve an acceptable clock skew. In addition, the custom fourth-level buffers may also increase or inefficiently utilize the area of the buffer block 201.